1. Field of the Invention
The present invention relates to a Built-In Self Test (BIST) circuit for a Large Scale Integrated (LSI) memory built in a LSI incorporating the LSI memory such as a Dynamic Random Access memory (DRAM), a Static Random Access Memory (SRAM), a Flash memory and the like.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a configuration of a conventional LSI incorporating a LSI memory. In FIG. 1, the reference number 51 designates a memory cell array such as a DRAM, a SRAM, a Flash memory, and the like. The reference number 52 denotes an internal circuit for reading data stored in the memory cell array 51 and for performing a predetermined function under the control of a CPU (omitted from FIG. 1). The reference numbers 53 and 54 indicate selectors for changing data paths, namely, for connecting the internal circuit 52 to the memory cell array 51 in order to transfer data between them during a normal operation mode, and for connecting a control signal input terminal and a test data input terminal to the memory cell array 51 in order to transfer control data and test data to the memory cell array 51 and to transfer test results from the memory cell array 51 to an external tester (omitted from FIG. 1) through a test data output terminal during a test operation mode.
During the test operation mode for the memory cell array 51 incorporated in the conventional LSI shown in FIG. 1, the control signal input terminal, the test data input terminal, the test data output terminal, and the selectors 53 and 54 are connected to the external tester (not shown) in order to perform the operation test of the memory cell array 51.
Next, a description will be given of the operation of the conventional LSI comprising the LSI memory.
During the operation test for the memory cell array 51, the external tester transfers a control signal to both the selectors 53 and 54 through the control signal input terminal. This transferring of the control signal enters the state in which the external tester may control the operation of the memory cell array 51.
Next, when receiving input the control signals from the external tester, both the selectors 53 and 54 disconnect the memory cell array 51 from the internal circuit 52, and connect the memory cell array 51 to the external tester through the test data input terminal and the test data output terminal.
Next, the external tester generates and outputs the test data to the memory cell array 51 through the test data input terminal. After this, the test data from the memory cell array 51 are transferred to the external tester through the test data output terminal. The external tester checks the test data from the memory cell array 51 whether the memory cell array 51 operates correctly or not.
Since the conventional LSI incorporating the memory cell array 51 such as a DRAM, a SRAM, a flash memory, and the like has the configuration described above, when performing the operation test such as a AT-speed memory test for the built-in memory cell array 51, it must be required to install a plurality of test data input terminals and a plurality of test data output terminals only for the test operation in addition to data input/output terminals only for the normal operation mode. For example, it must be required to install several ten or several hundred test data input terminals and test data output terminals for the test operation of the memory cell array. This causes to increase the number of terminals in the LSI and to reduce the circuit area in which internal circuits are formed, and further to increase the fabrication cost of the LSI.
Further, external testers are usually expensive devices. When the number of test terminals in a LSI is increased, the cost of the tester is also increased. As a result, this causes to increase the fabrication cost.
Moreover, since it is required to use a clock signal of a higher frequency for testing the reliability of the memory cell array 51, it is required to use the external tester capable of outputting the clock signal of a higher frequency. Therefore, this causes to increase the cost of the external tester, and to increase the fabrication cost of the LSI.
Furthermore, when logic circuits such as the internal circuit 52 are tested in addition to the memory cell array 51, it must be required to use a memory logic tester that is higher expensive in cost or to use both testers for the memory cell array 51 and the logic circuit, respectively. Therefore, this causes to increase the fabrication cost of the LSI.
Accordingly, an object of the present invention is, with due consideration to the drawbacks of the conventional technique, to provide a Built-in Self Test (BIST) circuit built in a LSI incorporating a large scale integrated memory such as a DRAM, a SRAM, a flash memory, and the like. The BIST circuit can perform the test operation for the large scale integrated memory including the generation of test data, the comparison of the test data, the detection of a faulty memory cell in the large scale integrated memory, and the self-repairing operation for the faulty memory cell.
In accordance with a preferred embodiment of the present invention, a Built-In Self Test (BIST) circuit for a Large Scale Integrated (LSI) memory built in a LSI incorporating the LSI memory, comprises a BIST controller for controlling an operation test for a memory cell array forming the LSI memory having a plurality of memory cells, a test pattern generator storing micro codes to be used for generation of test pattern data for executing the micro codes based on an instruction transferred from the BIST controller in order to generate the test pattern data and expected data and for outputting the test patterns and the expected data, a comparator for comparing the test pattern data outputted from the memory cell array, that have read the test pattern data supplied from the test pattern generator, with the expected data, a GO/NG register for storing data indicating whether the operation of the memory cell array has been performed normally or abnormally based on the comparison result of the comparator and outputting the data, an error information register for storing information regarding a bit line and a word line at which a faulty memory cell is formed when the comparison result from the comparator indicates that the memory cell array has operated abnormally, and a selector for selectively outputting the data and the information stored in the GO/NG register and the error information register to external devices. By using the configuration described above, the number of terminals of the LSI may be decreased and the test operation for the memory cell array in the LSI may be performed efficiently, so that the fabrication cost of the LSI may be also reduced.
The BIST circuit for the LSI memory built in the LSI incorporating the LSI memory as another preferred embodiment according to the present invention further comprises a repair code generator/register, that is incorporated in the BIST circuit instead of the error information register, for generating a repair code regarding information of a redundancy memory cell built in the LSI in advance to be used instead of the faulty memory cell when the comparison result from the comparator indicates that the memory cell array has operated abnormally. In the BIST circuit, the selector selectively outputs the repair code stored in the repair code generator/register and the data stored in the GO/NG register. By using the configuration described above, the number of terminals of the LSI may be decreased and the test operation of the memory cell array in the LSI may be performed efficiently in order to generate data for avoiding the use of the faulty memory cell, so that the fabrication cost of the LSI may be also reduced.
In accordance with another preferred embodiment of the present invention, a Built-In Self Test (BIST) circuit for a Large Scale Integrated (LSI) memory built in a LSI incorporating the LSI memory, comprises a BIST controller for controlling an operation test for a memory cell array forming the LSI memory having a plurality of memory cells, a test pattern generator storing micro codes to be used for generation of test pattern data for executing the micro codes based on an instruction transferred from the BIST controller in order to generate the test pattern data and expected data and for outputting the test patterns and the expected data, a comparator for comparing the test pattern data outputted from the memory cell array, that have read the test pattern data supplied from the test pattern generator, with the expected data, a GO/NG register for storing data indicating whether the operation of the memory cell array has been performed normally or abnormally based on the comparison result of the comparator and outputting the data, a repair code generator/register for generating a repair code regarding a bit line and a word line at which a faulty memory cell is formed when the comparison result from the comparator indicates that the memory cell array has operated abnormally, and a self repair circuit for reading the data stored in the repair code generator/register and for performing a repair operation in which the faulty memory cell is replaced with a redundancy memory circuit that has been built in the memory cell array in advance and the redundancy memory cell is activated. By using the configuration described above, the number of terminals to be used for the test operation of the memory cell array in the LSI may be decreased and the operation test for the memory cell array may be performed efficiently in order to generate repair data for repairing the faulty memory cell and to use the redundancy memory cell instead of the faulty memory cell, so that the fabrication cost of the LSI may be also reduced.
The BIST circuit for the LSI memory built in the LSI incorporating the LSI memory as another preferred embodiment according to the present invention further comprises a phase locked loop (PLL) for receiving an external clock signal supplied externally, for generating an internal clock signal of a predetermined frequency based on the received external clock signal, and for outputting the internal clock signal into the BIST controller. By using the configuration described above, it is possible to generate the internal clock signal of an optimum high frequency for the test operation, so that it is possible to execute the test operation such as AT-speed memory test for the memory cell array, even if an external tester for supplying an external clock signal of a low frequency.